Error: 'Primary clock master is not ready' message

Symptom

When there are multiple boards in a system that is being started using oamsys, a message 'Primary clock master is not ready' may appear.

Below is the oamsys output showing the full message:

Mon May 10 12:13:26 - CLKEVN_INFO INFO Board 1 "CG_6565 - 1"
Segm 1: Primary clock master is not ready. Configuration postponed.
Mon May 10 12:13:26 - CLKEVN_CONFIGURED INFO Board 0 "CG_6565_8 - 0"
Clock Mode = MASTER_A, Source = OSCILLATOR
Mon May 10 12:13:26 - CLKEVN_CONFIGURED INFO Board 1 "CG_6565 - 1"
Clock Mode = SLAVE, Source = A_CLOCK

Reason for the issue

This message may occur when there are multiple boards in the system and one board is configured as the H.100 clock master and the other boards are configured as slave boards.  This message means that the clock on the H.100 bus is not available, so the slave boards cannot sync up to the clock signal properly now, but they will try again later ('Configuration postponed').  

Note that the board with the lowest board number (e.g. board 0) does not always finish booting up first; the boot order depends on a system's PCI bus architecture, so the most common reason for this message occurring is that the slave board (e.g. board 1) boots up before the master board (e.g. board 0). In this case there is no valid clock on the bus yet and the message occurs on the slave board during board booting process.

Fix / Solution

This message can be ignored and no additional steps are required to resolve this as the slave boards will check the clock on the H.100 bus again later, and sync up to it when it is available. To confirm that all the boards' clocking parameters are configured properly once all the boards are booted,  run 'showclks' to show the clocking status for every board in the system. 

Product List

Dialogic CG Series Media Boards